Image sensor

ABSTRACT

An image sensor includes a pixel array in which a plurality of pixels, first and second row selection lines separated from each other, and first and second column lines separated from each other are disposed and a column selecting circuit configured to connect the first and second column lines using a column selection signal. The pixel array includes a first pixel which is connected to the first row selection line and the first column line and a second pixel which is disposed in the same row as the first pixel and connected to the second row selection line and the second column line.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation application of and claims priorityunder 35 U.S.C. §§120,121 to U.S. application Ser. No. 14/513,575 filedOct. 14, 2014, which claims priority from Korean Patent Application No.10-2014-0002421 filed on Jan. 8, 2014 in the Korean IntellectualProperty Office, the entire contents of each of which are herebyincorporated herein by reference.

BACKGROUND

1. Field

At least some example embodiments relate to an image sensor.

2. Description of the Related Art

An image sensor is one of the semiconductor devices that convert opticalinformation into an electrical signal. Examples of the image sensorinclude a charge coupled device (CCD) image sensor and a complementarymetal-oxide semiconductor (CMOS) image sensor.

Research is being conducted on an image sensor that performs both a fullmode operation and a binning mode operation.

The full mode operation is an operation of sensing an image usinginformation of all pixels included in a pixel array. On the other hand,the binning mode operation is an operation of collecting information ofselected pixels and sensing an image using the collected information.

SUMMARY

At least some example embodiments provide an image sensor which canreliably perform wide dynamic range (WDR) and auto focusing even in abinning mode operation.

However, example embodiments are not restricted to the one set forthherein.

According to an example embodiment, there is provided an image sensorincluding a pixel array including a plurality of pixels including atleast a first pixel and a second pixel, first and second row selectionlines separated from each other, and first and second column linesseparated from each other, and a column selecting circuit configured toconnect the first and second column lines using a column selectionsignal, the first pixel connected to the first row selection line andthe first column line, and the second pixel being in the same row as thefirst pixel and connected to the second row selection line and thesecond column line.

According to another example embodiment, there is provided an imagesensor including a pixel array including a plurality of pixels, firstand second row selection lines separated from each other, and columnlines intersecting the first and second row selection lines, a rowscanning circuit configured to control the first and second rowselection lines, and a sampling circuit configured to receive outputs ofthe column lines and convert the received outputs into digital signals,the first and second row selection lines being in each row of the pixelarray, and at least one select transistor in a number of the pluralityof pixels is connected to one of the first and second row selectionlines.

According to an example embodiment, there is provided an image sensorincluding a pixel array including a plurality of pixels having at leasta first pixel, a second pixel and a third pixel, first and second rowselection lines separated from each other, and first and second columnlines separated from each other are disposed, the first pixel of theplurality of pixels is connected to the first row selection line and thefirst column line, the second pixel of the plurality of pixels isconnected to the first column line and the second row selection line,and the third pixel of the plurality of pixels is in the same row of thepixel array as the second pixel and connected to the first row selectionline and the second column line.

According to an example embodiment, there is provided an image sensorincluding a pixel array including a plurality of pixels in columns andfirst and second column selection lines are disposed in each column ofthe pixels, a column selecting circuit configured to select at least oneof the first and second column selection lines in each column of thepixels, and a sampling circuit configured to receive an output of theselected column selection line and converts the received output into adigital signal.

At least one example embodiment discloses an image sensor including apixel array having rows and columns of pixels, the rows connected tofirst and second selection lines and the pixel array having firstexposure pixels and second exposure pixels, a control circuit configuredto supply at least one control signal to the pixels such that anexposure time of the first exposure pixels is greater than an exposuretime of the second exposure pixels, and a column selecting circuitconfigured to connect a number of the columns of pixels based on anoperating mode of the image sensor.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects and features of example embodiments willbecome more apparent by describing in detail embodiments thereof withreference to the attached drawings, in which:

FIG. 1 is a block diagram of an image sensor according to an exampleembodiment;

FIG. 2 is a circuit diagram of a pixel array and a column selectingcircuit of FIG. 1;

FIGS. 3A and 3B are circuit diagrams of pixels included in the pixelarray of FIG. 2;

FIG. 4 is a detailed block diagram of a sampling circuit of FIG. 1;

FIG. 5 is a timing diagram illustrating the full mode operation of theimage sensor of FIG. 1;

FIG. 6 is a timing diagram illustrating the binning mode operation ofthe image sensor of FIG. 1;

FIG. 7 is a diagram illustrating pixel arrangement in a case where theimage sensor of FIG. 1 performs the binning mode operation;

FIG. 8 is a circuit diagram of an image sensor according to anotherexample embodiment;

FIG. 9 is a circuit diagram of pixels included in a pixel array of FIG.8;

FIG. 10 is a timing diagram illustrating the full mode operation of theimage sensor of FIG. 8;

FIG. 11 is a timing diagram illustrating the binning mode operation ofthe image sensor of FIG. 8;

FIG. 12 is a circuit diagram of an image sensor according to anotherexample embodiment;

FIG. 13 is a diagram illustrating the structure of sensing pixelsincluded in a pixel array of FIG. 12;

FIG. 14 is a diagram illustrating the structure of phase-differencedetection pixels included in the pixel array of FIG. 12;

FIGS. 15 through 17 are diagrams illustrating a process of performingauto-focusing using the phase-difference detection pixels of FIG. 14;

FIG. 18 is a timing diagram illustrating the full mode operation of theimage sensor of FIG. 12;

FIG. 19 is a timing diagram illustrating the binning mode operation ofthe image sensor of FIG. 12;

FIG. 20 is a diagram illustrating pixel arrangement in a case where theimage sensor of FIG. 12 performs the binning mode operation;

FIG. 21 is a circuit diagram of an image sensor according to anotherexample embodiment;

FIG. 22 is a block diagram of an example of a digital camera using animage sensor;

FIG. 23 is a block diagram of an example of a computing system using animage sensor; and

FIG. 24 is a block diagram illustrating an example of interfaces used inthe computing system of FIG. 23.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Advantages and features of example embodiments and methods ofaccomplishing the same may be understood more readily by reference tothe following detailed description of example embodiments and theaccompanying drawings. Example embodiments may, however, be embodied inmany different forms and should not be construed as being limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete and will fully conveythe concept of example embodiments to those skilled in the art, andexample embodiments will only be defined by the appended claims. In thedrawings, the thickness of layers and regions are exaggerated forclarity.

It will be understood that when an element or layer is referred to asbeing “on” or “connected to” another element or layer, it can bedirectly on or connected to the other element or layer or interveningelements or layers may be present. In contrast, when an element isreferred to as being “directly on” or “directly connected to” anotherelement or layer, there are no intervening elements or layers presentLike numbers refer to like elements throughout. As used herein, the term“and/or” includes any and all combinations of one or more of theassociated listed items.

The use of the terms “a” and “an” and “the” and similar referents in thecontext of describing example embodiments (especially in the context ofthe following claims) are to be construed to cover both the singular andthe plural, unless otherwise indicated herein or clearly contradicted bycontext. The terms “comprising,” “having,” “including,” and “containing”are to be construed as open-ended terms (i.e., meaning “including, butnot limited to,”) unless otherwise noted.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another element. Thus, for example, a first element, afirst component or a first section discussed below could be termed asecond element, a second component or a second section without departingfrom the teachings of example embodiments.

Unless defined otherwise, all technical and scientific terms used hereinhave the same meaning as commonly understood by one of ordinary skill inthe art to which example embodiments belong. It is noted that the use ofany and all examples, or exemplary terms provided herein is intendedmerely to better illuminate example embodiments and is not a limitationon the scope of example embodiments unless otherwise specified. Further,unless defined otherwise, all terms defined in generally useddictionaries may not be overly interpreted.

An image sensor according to an example embodiment will now be describedwith reference to FIGS. 1 through 4.

FIG. 1 is a block diagram of an image sensor 1 according to an exampleembodiment. FIG. 2 is a circuit diagram of a pixel array 110 and acolumn selecting circuit 120 of FIG. 1. FIGS. 3A and 3B are circuitdiagrams of pixels included in the pixel array 110 of FIG. 2. FIG. 4 isa detailed block diagram of a sampling circuit 130 of FIG. 1.

Referring to FIG. 1, the image sensor 1 includes the pixel array 110,the column selecting circuit 120, a timing control circuit 160, a rowscanning circuit 150, a column scanning circuit 140, a reference signalgenerator 170, and the sampling circuit 130.

The pixel array 110 may include a plurality of pixels. The pixels may bearranged in a matrix pattern. Each of the pixels may have a 3-transistorstructure, a 4-transistor structure, a 5-transistor structure, a6-transistor structure, or the like according to the number oftransistors included in a signal generating circuit.

Referring to FIG. 2, first and second row selection lines SEL and SELXseparated from each other may be provided in each row of the pixel array110. A plurality of column lines C1 through C7 separated from each othermay be provided in a plurality of columns, respectively. In an example,if the pixel array 110 includes (M×N) pixels (where M and N are integersof two or more), M first row selection lines SEL, M second row selectionlines SELX, and N column lines C1 through C7 may be provided in thepixel array 110.

Row addressing and row scanning of the pixel array 110 may be controlledby the row scanning circuit 150 through the first and second rowselection lines SEL and SELX, and column addressing and column scanningof the pixel array 110 may be controlled by the column scanning circuit140 through the column lines C1 through C7.

If the image sensor 1 employs Bayer pattern technology, the pixelswithin the active pixel array 110 may be arranged to receive red light,green light and blue light, respectively.

In FIG. 1, the pixels within the pixel array 110 may be used for widedynamic range (WDR). In the WDR, pixels that receive the red light andthe blue light may be used to determine the color of a sensed image, andpixels that receive the green light may be used to determine thebrightness of the sensed image. Therefore, the pixels that receive thered light and the blue light may respectively include long exposurepixels R and B and short exposure pixels r and b, and the pixels thatreceive the green light may include first-type pixels Gr and second-typepixels Gb.

In addition, the pixels within the pixel array 110 may be arranged in achess mosaic pattern. Accordingly, the long exposure pixels R and B andthe short exposure pixels r and b may be arranged alternately with thefirst-type pixels Gr and the second-type pixels Gb interposedtherebetween. Specifically, a second pixel P2, a fourth pixel P4, asixth pixel P6, a sixteenth pixel P16, an eighteenth pixel P18 and atwentieth pixel P20 which are the second-type pixels Gb may respectivelybe disposed between a first pixel P1, a fifth pixel P5, a seventeenthpixel P17 and twenty first pixel P21 which are the long exposure pixelsB receiving the blue light and a third pixel P3, a seventh pixel P7, afifteenth pixel P15 and a nineteenth pixel P19 which are the shortexposure pixels b receiving the blue light. In addition, an eighth pixelP8, a tenth pixel P10, a twelfth pixel P12, a fourteenth pixel P14, atwenty second pixel P22, a twenty fourth pixel P24, a twenty sixth pixelP26 and a twenty eighth pixel P28 which are the first-type pixels Gr mayrespectively be disposed between a ninth pixel P9, a thirteenth pixelP13 and a twenty fifth pixel P25 which are the long exposure pixels Rreceiving the red light and an eleventh pixel P11, a twenty third pixelP23 and a twenty seventh pixel P27 which are the short exposure pixels rreceiving the red light.

However, example embodiments are not limited to the above arrangement,and the arrangement of the pixels P1 through P28 within the pixel array110 can be changed as desired. For example, in some other exampleembodiments, the pixels P1 through P28 within the pixel array 110 may beconfigured to receive magenta (Mg) light, yellow (Y) light, cyan (Cy)light, and/or white (W) light, respectively.

In FIG. 1, pixels disposed in the same row may be connected to differentrow selection lines SEL and SELX.

Specifically, pixels P1, P2, P4, P6 and P7 of the first through seventhpixels P1 through P7 disposed in an i^(th) row (where i is a naturalnumber) may be connected to the first row selection line SEL, and theother pixels P3 and P5 may be connected to the second row selection lineSELX. Pixels P8, P9, P10, P12 and P14 of the eighth through fourteenthpixels P8 through P14 disposed in an (i+1)^(th) row may be connected tothe first row selection line SEL, and the other pixels P11 and P13 maybe connected to the second row selection line SELX. Pixels P16, P17,P18, P19 and P20 of the fifteenth through twenty first pixels P15through P21 disposed in an (i+2)^(th) row may be connected to the firstrow selection line SEL, and the other pixels P15 and P21 may beconnected to the second row selection line SELX. Pixels P22, P24, P25,P26, P27 and P28 of the twenty second through twenty eighth pixels P22through P28 disposed in an (i+3)^(th) row may be connected to the firstrow selection line SEL, and the other pixel P23 may be connected to thesecond row selection line SELX.

The pixels P1 through P28 included in the pixel array 110 are arrangedas described above to enable the image sensor 1 to perform WDR even whenoperating in a binning mode. This will be described in greater detaillater.

The pixels P1 through P28 included in the pixel array 110 may be dividedinto pixels connected to the first row selection line SEL and pixelsconnected to the second row selection line SELX as described above.

Referring to FIG. 3A, a pixel (e.g., the first pixel P1) connected tothe first row selection line SEL may include a photodiode PD1, atransfer transistor TR1, a reset transistor TR2, a drive transistor TR3,and a select transistor TR4. A pixel having a 4-transistor structurewill hereinafter be described as an example, but example embodiments arenot limited to this example. The pixel structure can also be changed toa 3-transistor structure, a 5-transistor structure, a 6-transistorstructure, etc., as described above

The photodiode PD1 is a light-receiving device that receives an externaloptical image. The photodiode PD1 may generate photocharges inproportion to incident light. In FIG. 3A, the photodiode PD1 isillustrated as an example of the light-receiving device. However,example embodiments are not limited thereto, and the form of thelight-receiving device can be changed as desired.

The photodiode PD1 may be connected between the transfer transistor TR1and a ground terminal GND.

The transfer transistor TR1 may transfer photocharges generated by thephotodiode PD1 to a gate terminal of the drive transistor TR3 via afloating diffusion node FD. To this end, the transfer transistor TR1 mayhave a drain terminal connected to the floating diffusion node FD, asource terminal connected to the photodiode PD1, and a gate terminalconnected to the row scanning circuit 150 (see FIG. 2). When receiving atransfer control signal TG(i) (since the first pixel P1 is disposed inthe i^(th) row, the transfer control signal TG(i) for the i^(th) row isprovided to the first pixel P1) from the row scanning circuit 150 (seeFIG. 2), the transfer transistor TR1 may be turned on to provide anoutput of the photodiode PD1 to the floating diffusion node FD.

The reset transistor TR2 may apply a reset voltage to the gate terminalof the drive transistor TR3. To this end, the reset transistor TR2 mayhave a drain terminal connected to a driving power source terminal VDD,a source terminal connected to the floating diffusion node FD, and agate terminal connected to the row scanning circuit 150 (see FIG. 2).When receiving a reset control signal RS from the row scanning circuit150 (see FIG. 2), the reset transistor TR2 may be turned on to providean output of the power source terminal VDD to the gate terminal of thedrive transistor TR3. When the output of the power source terminal VDDis provided to the gate terminal of the drive transistor TR3, the drivetransistor TR3 may be completely turned on. As a result, an output ofthe drive transistor TR3 may be reset.

The drive transistor TR3 generates a source-drain current in proportionto the amount of photocharges transmitted to the gate terminal thereof.Specifically, the floating diffusion node FD generates a floatingdiffusion voltage VFD proportional to the amount of photochargesgenerated by the photodiode PD1. When the floating diffusion voltage VFDis applied to the gate terminal of the drive transistor TR3, thesource-drain current proportional to the amount of photocharges may begenerated.

For this operation, the drive transistor TR3 may have a drain terminalconnected to the power source terminal VDD, a source terminal connectedto a drain terminal of the select transistor TR4, and the gate terminalconnected to the floating diffusion node FD which is a common terminalof the drain terminal of the transfer transistor TR1 and the sourceterminal of the reset transistor TR2.

The select transistor TR4 may transfer a current generated by the drivetransistor TR3 to the column line C1. To this end, the select transistorTR4 may have the drain terminal connected to the source terminal of thedrive transistor TR3, a source terminal connected to the column line C1,and the gate terminal connected to the first row selection line SEL. Asdescribed above, the first pixel P1 is connected to the first rowselection line SEL but not to the second row selection line SELX.Therefore, the second row selection line SELX may not be connected tothe gate terminal of the select transistor TR4.

In the above structure, the select transistor TR may be gated by asignal transmitted to the first row selection line SEL and output asource-drain current (e.g., an image signal) generated by the drivetransistor TR3 to the column line C1.

It should be understood that the row scanning circuit 150 is configuredto supply the transfer control signal TG and reset signal RS such thatthe long exposure pixels B and R have a longer exposure time than theshort exposure pixels r and b.

Referring to FIG. 3B, a pixel (e.g., the eleventh pixel P11) connectedto the second row selection line SELX may include a photodiode PD2, atransfer transistor TR5, a reset transistor TR6, a drive transistor TR7,and a select transistor TR8.

The photodiode PD2, the reset transistor TR6, and the drive transistorTR7 are identical to those described above, and thus a redundantdescription thereof will be omitted.

Since the eleventh pixel P11 is disposed in the (i+1)^(th) row, atransfer control signal TG(i+1) provided to a gate terminal of thetransfer transistor TR5 is different from the transfer control signalTG(i) provided to the gate terminal of the transfer transistor TR1 ofthe first pixel P1 described above.

In addition, since the eleventh pixel P11 is connected to the second rowselection line SELX but not to the first row selection line SEL, thefirst row selection line SEL may not be connected to a gate terminal ofthe select transistor TR8.

In the above structure, the select transistor TR8 may be gated by asignal transmitted to the second row selection line SELX and output asource-drain current (e.g., an image signal) generated by the drivetransistor TR7 to the column line C4.

Referring back to FIGS. 1 and 2, the column selecting circuit 120 mayprovide outputs from the plurality of column lines C1-C7 in the pixelarray 110 to the sampling circuit 130. The column selecting circuit 120may connect at least two of the column lines within the pixel array 110using a column selection signal AVG in order to support the binning modeoperation of the image sensor 1.

In some example embodiments, the column selecting circuit 120 mayinclude a column selecting signal generator 122 which generates thecolumn selection signal AVG. However, example embodiments are notlimited thereto. The column selection signal AVG may also not begenerated by the column selecting circuit 120 but may be provided by,e.g., the row scanning circuit 150.

In FIG. 2, the column selecting circuit 120 includes a first switch S1which can connect the first column line C1 and the third column line C3,a second switch S2 which can connect the second column line C2 and thefourth column line C4, and a third switch S3 which can connect the fifthcolumn line C5 and the seventh column line C7. The specific operation ofthe column selecting circuit 120 will be described later.

Referring back to FIG. 1, the reference signal generator 170 maygenerate a reference signal VRAMP and provide the reference signal VRAMPto the sampling circuit 130. In the current embodiment, the referencesignal VRAMP may be in the form of a ramp.

The sampling circuit 130 may receive an output of the column selectingcircuit 120 and perform correlation double sampling (CDS) andanalog-to-digital conversion once or twice. The sampling circuit 130 maybe controlled by the timing control circuit 160 and performanalog-to-digital conversion in each row scan period of the pixel array110 by the row scanning circuit 150.

Referring to FIG. 4, the sampling circuit 130 may include a plurality ofanalog-to-digital converters (ADCs), each including a comparator 131, acounter 132, and a latch 133.

The comparator 131 may compare an output of the column line C1 with thereference signal VRAMP and output a value of the comparison result. Thecounter 132 may perform counting based on the comparison result value ofthe comparator 131 and provide a value of the counting result to thelatch 133. The latch 133 may store the counting result value of thecounter 132 and output the counting result value in synchronizationwith, e.g., a clock signal. In this structure of the sampling circuit130, an analog signal (e.g., an analog image signal) output from thecolumn line C1 may be converted into a digital signal (e.g., a digitalimage signal).

Referring back to FIG. 1, the row scanning circuit 150 may control therow addressing and row scanning of the pixel array 110 in response tocontrol signals received from the timing control circuit 160. The rowscanning circuit 150 may transmit a signal for activating acorresponding row selection line SEL or SELX to the pixel array 110 inorder to select the corresponding row selection line SEL or SELX fromthe row selection lines SEL and SELX. The row scanning circuit 150 mayinclude a row decoder which selects a row selection line SEL or SELX inthe pixel array 110 and a row driver which transmits a signal foractivating the selected row selection line SEL or SELX.

The column scanning circuit 140 may control the column addressing andcolumn scanning of the pixel array 110 in response to control signalsreceived from the timing control circuit 160. The column scanningcircuit 140 may transmit a digital signal output from the samplingcircuit 130 to a digital signal processor (DSP), an image signalprocessor (ISP), or an external host.

For example, the column scanning circuit 140 may sequentially select theADCs within the sampling circuit 130 by outputting a horizontal scancontrol signal to the sampling circuit 130. In some example embodiments,the column scanning circuit 140 may include a column decoder whichselects one of the ADCs and a column driver which induces an output of aselected unit ADC to a horizontal transmission line.

The timing control circuit 160 may control the sampling circuit 130, thecolumn scanning circuit 140 and the row scanning circuit 150 and providecontrol signals (such as a clock signal and a timing control signal)required for the operations of the sampling circuit 130, the columnscanning circuit 140 and the row scanning circuit 150. The timingcontrol circuit 160 may include a logic control circuit, a phase lockloop (PLL) circuit, a timing control circuit, a communication interfacecircuit, etc.

The full mode operation of the image sensor 1 of FIG. 1 will now bedescribed with reference to FIGS. 2 and 5.

FIG. 5 is a timing diagram illustrating the full mode operation of theimage sensor 1 of FIG. 1.

Referring to FIGS. 2 and 5, in section A, the transfer control signalTG(i) for the i^(th) row is provided. In addition, a signal at a highlevel (hereinafter, the high level denotes a logical high level) isprovided to the first and second row selection lines SEL and SELX.Accordingly, image signals output from the pixels P1 through P7 disposedin the i^(th) row are provided to the column selecting circuit 120 viathe first through seventh column lines C1 through C7.

In the section A, since the column selection signal AVG is at a lowlevel (hereinafter, the low level denotes a logical low level), all ofthe first through third switches S1 through S3 included in the columnselecting circuit 120 are off. Therefore, outputs of the first throughseventh column lines C1 through C7 are provided to the sampling circuit130 without being combined with each other.

In section B, the transfer control signal TG(i+1) for the (i+1)^(th) rowis provided. In addition, a high-level signal is provided to the firstand second row selection lines SEL and SELX. Accordingly, image signalsoutput from the pixels P8 through P14 disposed in the (i+1)^(th) row areprovided to the column selecting circuit 120 via the first throughseventh column lines C1 through C7.

In the section B, since the column selection signal AVG is at a lowlevel, all of the first through third switches Si through S3 included inthe column selecting circuit 120 are off. Therefore, outputs of thefirst through seventh column lines C1 through C7 are provided to thesampling circuit 130 without being combined with each other.

In sections C and D, an image signal output from each of the pixels P15through P28 is also provided to the sampling circuit 130 through thesame process the process as described above. Therefore, the image sensor1 can perform the full-mode operation, that is, perform image sensingusing all pixels P1 through P28 included in the pixel array 110.

In FIG. 5, a high-level signal is provided in the form of a pulse to thefirst and second row selection lines SEL and SELX over the sections Athrough D. However, example embodiments are not limited thereto. Thatis, in some example embodiments, a high-level signal may be continuouslyprovided to the first and second row selection lines SEL and SELX overthe sections A through D.

In addition, in FIG. 5, the transfer control signals TG(i) throughTG(i+3) are sequentially transmitted to the i^(th) through (i+3)^(th)rows, respectively. However, example embodiments are not limitedthereto. In some other example embodiments n, a high-level signal may betransmitted to the first and second row selection lines SEL and SELX ofthe i^(th) through (i+3)^(th) rows sequentially.

Specifically, in the section A, a high-level signal may be provided tothe first and second row selection lines SEL and SELX disposed in thei^(th) row, and a low-level signal may be provided to the first andsecond row selection lines SEL and SELX disposed in the (i+1)^(th)through (i+3)^(th) rows. Accordingly, image signals output from thepixels P1 through P7 disposed in the i^(th) row may be provided to thesampling circuit 130 via the first through seventh column lines C1through C7.

In the section B, a high-level signal may be provided to the first andsecond row selection lines SEL and SELX disposed in the (i+1)^(th) row,and a low-level signal may be provided to the first and second rowselection lines SEL and SELX disposed in the i^(th), (i+2)^(th) and(i+3)^(th) rows. Accordingly, image signals output from the pixels P8through P14 disposed in the (i+1)^(th) row may be provided to thesampling circuit 130 via the first through seventh column lines C1through C7.

In the section C, a high-level signal may be provided to the first andsecond row selection lines SEL and SELX disposed in the (i+2)^(th) row,and a low-level signal may be provided to the first and second rowselection lines SEL and SELX disposed in the i^(th), (i+1)^(th), and(i+3)^(th) rows. Accordingly, image signals output from the pixels P15through P21 disposed in the (i+2)^(th) row may be provided to thesampling circuit 130 via the first through seventh column lines C1through C7.

Lastly, in the section D, a high-level signal may be provided to thefirst and second row selection lines SEL and SELX disposed in the(i+3)^(th) row, and a low-level signal may be provided to the first andsecond row selection lines SEL and SELX disposed in the i^(th) through(i+2)^(th) rows. Accordingly, image signals output from the pixels P22through P28 disposed in the (i+3)^(th) row may be provided to thesampling circuit 130 via the first through seventh column lines C1through C7.

In other words, the way each row of the pixel array 110 is selected tooutput an image signal is not limited to a particular way.

The binning mode operation of the image sensor 1 of FIG. 1 will now bedescribed with reference to FIGS. 2, 6 and 7.

FIG. 6 is a timing diagram illustrating the binning mode operation ofthe image sensor 1 of FIG. 1. FIG. 7 is a diagram illustrating pixelarrangement in a case where the image sensor 1 of FIG. 1 performs thebinning mode operation.

The binning mode operation of the image sensor 1 will now be describedusing a 2×2 binning mode operation as an example. However, exampleembodiments are not limited to this example. That is, the image sensor 1can be modified to perform a 3×3 binning mode operation, a 4×4 binningmode operation, etc.

In the 2×2 binning mode operation, nine pixels that form a square aredefined as one unit pixel. Therefore, the pixels P1 through P28illustrated in FIG. 2 may be divided into unit pixels in the 2×2 binningmode operation as shown in Table 1 below.

TABLE 1 Unit Pixel UPpq (p is a row, and q is a column) Pixels IncludedUP11 P1~P3 P8~P10 P15~P17 UP12 P2~P4 P9~P11 P16~P18 UP13 P5~P7 P12~P14P19~P21 UP21 P8~P10 P15~P17 P22~P24 UP22 P9~P11 P16~P18 P23~P25 UP23P12~P14 P19~P21 P26~P28

Referring to FIGS. 2 and 6, in section E, the transfer control signalsTG(i) and TG(i+2) for the i^(th) row and the (i+2)^(th) row areprovided. In addition, a high-level signal is provided to the first rowselection line SEL, and a low-level signal is provided to the second rowselection line SELX.

Accordingly, image signals output from the pixels P1, P2, P4, P6 and P7connected to the first row selection line SEL among the pixels P1through P7 disposed in the i^(th) row are provided to the columnselecting circuit 120 via the first through seventh column lines C1through C7. In addition, image signals output from the pixels P16, P17,P18, P19 and P20 connected to the first row selection line SEL among thepixels P15 through P21 disposed in the (i+2)^(th) row are provided tothe column selecting circuit 120 via the first through seventh columnlines C1 through C7.

In the section E, since the column selection signal AVG is at a highlevel, all of the first through third switches S1 through S3 included inthe column selecting circuit 120 are on. Therefore, an output of thefirst column line C1 and an output of the third column line C3 arecombined and provided accordingly to the sampling circuit 130, an outputof the second column line C2 and an output of the fourth column line C4are combined and provided accordingly to the sampling circuit 130, andan output of the fifth column line C5 and an output of the seventhcolumn line C7 are combined and provided accordingly to the samplingcircuit 130.

In section F, the transfer control signals TG(i+1) and TG(i+3) for the(i+1)^(th) row and the (i+3)^(th) row are provided. In addition, ahigh-level signal is provided to the first row selection line SEL, and alow-level signal is provided to the second row selection line SELX.

Accordingly, image signals output from the pixels P8, P9, P10, P12 andP14 connected to the first row selection line SEL among the pixels P8through P14 disposed in the (i+1)^(th) row are provided to the columnselecting circuit 120 via the first through seventh column lines C1through C7. In addition, image signals output from the pixels P22, P24,P25, P26, P27 and P28 connected to the first row selection line SELamong the pixels P22 through P28 disposed in the (i+3)^(th) row areprovided to the column selecting circuit 120 via the first throughseventh column lines C1 through C7.

In the section F, since the column selection signal AVG is at a highlevel, all of the first through third switches S1 through S3 included inthe column selecting circuit 120 are on. Therefore, an output of thefirst column line C1 and an output of the third column line C3 arecombined and provided accordingly to the sampling circuit 130, an outputof the second column line C2 and an output of the fourth column line C4are combined and provided accordingly to the sampling circuit 130, andan output of the fifth column line C5 and an output of the seventhcolumn line C7 are combined and provided accordingly to the samplingcircuit 130.

Based on these operations, pixels used in the binning mode operation maybe summarized by each unit pixel as shown in Table 2 below.

TABLE 2 Unit Pixel Pixels Used UP11(section E) P1 P17 UP12(section E)P2, P4 P16, P18 UP13(section E) P7 P19 UP21(section F) P8, P10 P22, P24UP22(section F) P9 P25 UP23(section F) P12, P14 P26, P28

An output of a unit pixel UP11 is related only to the first pixel P1 andthe seventeenth pixel P17 which are long exposure pixels B. That is, thethird pixel P3 and the fifteenth pixel P15 which are short exposurepixels b do not affect the output of the unit pixel UP11 because theyare not selected. Accordingly, the unit pixel UP11 may be used as a longexposure pixel B in WDR as illustrated in FIG. 7.

An output of a unit pixel UP12 is related to the second pixel P2, thefourth pixel P4, the sixteenth pixel P16 and the eighteenth pixel P18which are second-type pixels Gb. Accordingly, the unit pixel UP12 may beused as a second-type pixel Gb in WDR as illustrated in FIG. 7.

An output of a unit pixel UP13 is related only to the seventh pixel P7and the nineteenth pixel P19 which are short exposure pixels b. That is,the fifth pixel P5 and the twenty first pixel P21 which are longexposure pixels B do not affect the output of the unit pixel UP13because they are not selected. Accordingly, the unit pixel UP13 may beused as a short exposure pixel b in WDR as illustrated in FIG. 7.

An output of a unit pixel UP21 is related to the eighth pixel P8, thetenth pixel P10, the twenty second pixel P22 and the twenty fourth pixelP24 which are first-type pixels Gr. In addition, an output of a unitpixel UP23 is related to the twelfth pixel P12, the fourteenth pixelP14, the twenty sixth pixel P26 and the twenty eighth pixel P28 whichare first-type pixels Gr. Accordingly, the unit pixels UP21 and UP23 maybe used as first-type pixels Gr in WDR as illustrated in FIG. 7.

Lastly, an output of a unit pixel UP22 is related only to the ninthpixel P9 and the twenty fifth pixel P25 which are long exposure pixelsR. That is, the eleventh pixel P11 and the twenty third pixel P23 whichare short exposure pixels r do not affect the output of the unit pixelUP22 because they are not selected. Accordingly, the unit pixel UP22 maybe used as a long exposure pixel R in WDR as illustrated in FIG. 7.

Unlike in the image sensor 1, if outputs of the unit pixels UP11 throughUP13 and UP21 through UP23 are related to both outputs of the longexposure pixels B and R and outputs of the short exposure pixels b andr, reliable WDR cannot be performed in the binning mode operation usingthe unit pixels UP11 through UP13 and UP21 through UP23.

However, in the image sensor 1, the first and second row selection linesSEL and SELX separated from each other are provided in each row of thepixel array 110. Therefore, WDR can be performed using the unit pixelsUP11 through UP13 and UP21 through UP23 even in the binning modeoperation. That is, WDR can be performed reliably even in the binningmode operation without the addition of a circuit, which can increase themanufacturing cost of a product, to the image sensor 1.

In FIG. 6, each row of the pixel array 110 is controlled by the transfercontrol signal TG(i), TG(i+1), TG(i+2) or TG(i+3). However, exampleembodiments are not limited thereto. As described above, each row of thepixel array 110 may also be controlled by a signal provided to the firstand second row selection lines SEL and SELX.

Specifically, in the section E, a high-level signal may be provided tothe first row selection line SEL disposed in the i^(th) row and the(i+2)^(th) row, and a low-level signal may be provided to the secondselection line SELX disposed in the i^(th) row and the (i+2)^(th) rowand to the first and second row selection lines SEL and SELX disposed inthe (i+1)^(th) row and the (i+3)^(th) row. Accordingly, the sameoperation as the operation described above with reference to FIG. 5 maybe performed.

In addition, in the section F, a high-level signal may be provided tothe first row selection line SEL disposed in the (i+1)^(th) row and the(i+3)^(th) row, and a low-level signal may be provided to the secondselection line SELX disposed in the (i+1)^(th) row and the (i+3)^(th)row and to the first and second row selection lines SEL and SELXdisposed in the i^(th) row and the (i+2)^(th) row. Accordingly, the sameoperation as the operation described above with reference to FIG. 5 maybe performed.

In other words, the way each row of the pixel array 110 is selected tooutput an image signal is not limited to a particular way.

An image sensor according to another example embodiment will now bedescribed with reference to FIGS. 8 and 9.

FIG. 8 is a circuit diagram of an image sensor 2 according to anotherexample embodiment. FIG. 9 is a circuit diagram of pixels included in apixel array 110 of FIG. 8. For simplicity, a redundant description ofelements identical to those in FIGS. 2-7 will be omitted.

Referring to FIG. 8, in the image sensor 2, first, second and third rowselection lines SEL, SELX and SELY separated from each other may beprovided in each row. In addition, pixels disposed in the same row maybe connected to different row selection lines SEL, SELX and SELY.

Specifically, some pixels P101, P102 and P107 of first through seventhpixels P1 through P7 disposed in an i^(th) row may be connected to thefirst row selection line SEL, some other pixels P103 and P105 may beconnected to the second row selection line SELX, and the other pixelsP104 and P106 may be connected to the third row selection line SELY.

Eighth through fourteenth pixels P8 through P14 disposed in an(i+1)^(th) row may share the first, second and third row selection linesSEL, SELX and SELY with the first through seventh pixels P101 throughP107 disposed in the i^(th) row.

That is, some pixels P108, P109 and P114 of the eighth throughfourteenth pixels P108 through P114 disposed in the (i+1)^(th) row mayshare the first row selection line SEL with the pixels P101, P102 andP107 disposed in the i^(th) row, some other pixels P110 and P112 mayshare the second row selection line SELX with the pixels P103 and P105disposed in the i^(th) row, and the other pixels P111 and P113 may sharethe third row selection line SELY with the pixels P104 and P106 disposedin the i^(th) row.

Two pixels disposed in the same column share the same row selection lineSEL, SELX or SELY because a plurality of pixels P101 through P128included in the image sensor 2 has a two-shared structure. This will bedescribed in greater detail later.

Some pixels P117, P118 and P119 of fifteenth through twenty first pixelsP115 through P121 disposed in an (i+2)^(th) row may be connected to thefirst row selection line SEL, some other pixels P115 and P121 may beconnected to the second row selection line SELX, and the other pixelsP116 and P120 may be connected to the third row selection line SELY.

Twenty second through twenty eighth pixels P122 through P128 disposed inan (i+3)^(th) row may share the first, second and third row selectionlines SEL, SELX and SELY with the fifteenth through twenty first pixelsP115 through P121 disposed in the (i+2)^(th) row.

That is, some pixels P124, P125 and P126 of the twenty second throughtwenty eighth pixels P122 through P128 disposed in the (i+3)^(th) rowmay share the first row selection line SEL with the pixels P117, P118and P119 disposed in the (i+2)^(th) row, some other pixels P122 and P128may share the second row selection line SELX with the pixels P115 andP121 disposed in the (i+2)^(th) row, and the other pixels P123 and P127may share the third row selection line SELY with the pixels P116 andP120 disposed in the (i+2)^(th) row.

The pixels P101 through P128 are arranged as described above to enablethe image sensor 2 to perform WDR even when operating in the binningmode. This will be described in greater detail later.

As described above, the image sensor 2 may be structured such that twopixels can share one select transistor. This will now be described ingreater detail with reference to FIG. 9.

Referring to FIG. 9, a photodiode PD0 included in the twenty secondpixel P122 and a photodiode PD1 included in the fifteenth pixel P115 maybe connected to transfer transistors TR0 and TR1, respectively. Transfercontrol signals TG(i+3) and TG(i+2) corresponding to rows in which thepixels P122 and P115 are disposed may be provided to gate terminals ofthe transfer transistors TR0 and TR1, respectively.

A reset control signal RS may be provided to a gate terminal of a resettransistor TR2. As illustrated in the drawing, the two pixels P122 andP115 may share the reset transistor TR2, a drive transistor TR3, and aselect transistor TR4. Since the twenty second pixel P122 and thefifteenth pixel P115 are connected to the second row selection line SELXas illustrated in FIG. 8, a gate terminal of the select transistor TR4may be connected to the second row selection line SELX.

In a substantially similar manner, a photodiode PD2 included in theeighth pixel P108 and a photodiode PD3 included in the first pixel P101may be connected to transfer transistors TR5 and TR6, respectively.Transfer control signals TG(i+1) and TG(i) corresponding to rows inwhich the pixels P108 and P101 are disposed may be provided to gateterminals of the transfer transistors TR5 and TR6, respectively.

As illustrated in the drawing, the two pixels P108 and P101 may share areset transistor TR7, a drive transistor TR8, and a select transistorTR9. Since the eighth pixel P108 and the first pixel P101 are connectedto the first row selection line SEL as illustrated in FIG. 8, a gateterminal of the select transistor TR9 may be connected to the first rowselection line SELX.

Although not specifically illustrated, two pixels (e.g., P104 and P111)sharing the third row selection line SELX may be structured in a similarway to the above pixels except that a gate terminal of a selecttransistor (not shown) shared by the two pixels is connected to thethird row selection line SELY, and thus a detailed description thereofwill be omitted.

The full mode operation of the image sensor 2 of FIG. 8 will now bedescribed with reference to FIGS. 8 and 10.

FIG. 10 is a timing diagram illustrating the full mode operation of theimage sensor 2 of FIG. 8.

Referring to FIGS. 8 and 10, in section G, the transfer control signalTG(i) for the i^(th) row is provided. In addition, a high-level signalis provided to the first, second and third row selection lines SEL, SELXand SELY. Accordingly, image signals output from the pixels P101 throughP107 disposed in the i^(th) row are provided to a column selectingcircuit 120 via first through seventh column lines C1 through C7.

In the section G, since a column selection signal AVG is at a low level,all of first through third switches S1 through S3 included in the columnselecting circuit 120 are off. Therefore, outputs of the first throughseventh column lines C1 through C7 are provided to a sampling circuit130 without being combined with each other.

In section H, the transfer control signal TG(i+1) for the (i+1)^(th) rowis provided. In addition, a high-level signal is provided to the first,second and third row selection lines SEL, SELX and SELY. Accordingly,image signals output from the pixels P108 through P114 disposed in the(i+1)^(th) row are provided to the column selecting circuit 120 via thefirst through seventh column lines C1 through C7.

In the section H, since the column selection signal AVG is at a lowlevel, all of the first through third switches S1 through S3 included inthe column selecting circuit 120 are off. Therefore, outputs of thefirst through seventh column lines C1 through C7 are provided to thesampling circuit 130 without being combined with each other.

In sections I and J, an image signal output from each of the pixels P115through P128 is also provided to the sampling circuit 130 through thesame process the process as described above. Therefore, the image sensor2 can perform the full-mode operation, that is, perform image sensingusing all pixels P101 through P128 included in the pixel array 110.

In FIG. 10, a high-level signal is provided in the form of a pulse tothe first, second and third row selection lines SEL, SELX and SELY overthe sections G through J. However, example embodiments are not limitedthereto. That is, in some example embodiments, a high-level signal maybe continuously provided to the first, second and third row selectionlines SEL, SELX and SELY over the sections G through J.

In addition, in FIG. 10, the transfer control signals TG(i) throughTG(i+3) are sequentially transmitted to the i^(th) through (i+3)^(th)rows, respectively. However, example embodiments are not limitedthereto. In some other example embodiments, a high-level signal may betransmitted to the first, second and third row selection lines SEL, SELXand SELY of the i^(th) through (i+3)^(th) rows sequentially. Since thisis similar to the description of FIG. 5, a redundant description thereofwill be omitted.

The binning mode operation of the image sensor 2 of FIG. 8 will now bedescribed with reference to FIGS. 8 and 11.

FIG. 11 is a timing diagram illustrating the binning mode operation ofthe image sensor 2 of FIG. 8.

The binning mode operation of the image sensor 2 will now be describedusing a 2×2 binning mode operation as an example, but exampleembodiments are not limited to this example.

Referring to FIGS. 8 and 11, in section K, the transfer control signalsTG(i) and TG(i+2) for the i^(th) row and the (i+2)^(th) row areprovided. In addition, a high-level signal is provided to the first rowselection line SEL and the third row selection line SELY, and alow-level signal is provided to the second row selection line SELX.

Accordingly, image signals output from the pixels P101, P102 and P107connected to the first row selection line SEL and image signals outputfrom the pixels P104 and P106 connected to the third row selection lineSELY among the pixels P101 through P107 disposed in the i^(th) row areprovided to the column selecting circuit 120 via the first throughseventh column lines C1 through C7. In addition, image signals outputfrom the pixels P117, P118 and P119 connected to the first row selectionline SEL and image signals output from the pixels P116 and P120connected to the third row selection line SELY among the pixels P115through P121 disposed in the (i+2)^(th) row are provided to the columnselecting circuit 120 via the first through seventh column lines C1through C7.

In the section K, since the column selection signal AVG is at a highlevel, all of the first through third switches S1 through S3 included inthe column selecting circuit 120 are on. Therefore, an output of thefirst column line C1 and an output of the third column line C3 arecombined and provided accordingly to the sampling circuit 130, an outputof the second column line C2 and an output of the fourth column line C4are combined and provided accordingly to the sampling circuit 130, andan output of the fifth column line C5 and an output of the seventhcolumn line C7 are combined and provided accordingly to the samplingcircuit 130.

In section L, the transfer control signals TG(i+1) and TG(i+3) for the(i+1)^(th) row and the (i+3)^(th) row are provided. In addition, ahigh-level signal is provided to the first row selection line SEL andthe second row selection line SELX, and a low-level signal is providedto the third row selection line SELY.

Accordingly, image signals output from the pixels P108, P109 and P114connected to the first row selection line SEL and image signals outputfrom the pixels P110 and P112 connected to the second row selection lineSELX among the pixels P108 through P114 disposed in the (i+1)^(th) roware provided to the column selecting circuit 120 via the first throughseventh column lines C1 through C7. In addition, image signals outputfrom the pixels P124, P125, P126 and P127 connected to the first rowselection line SEL and image signals output from the pixels P122 andP128 connected to the second row selection line SELX among the pixelsP122 through P128 disposed in the (i+4)^(th) row are provided to thecolumn selecting circuit 120 via the first through seventh column linesC1 through C7.

In the section L, since the column selection signal AVG is at a highlevel, all of the first through third switches S1 through S3 included inthe column selecting circuit 120 are on. Therefore, an output of thefirst column line C1 and an output of the third column line C3 arecombined and provided accordingly to the sampling circuit 130, an outputof the second column line C2 and an output of the fourth column line C4are combined and provided accordingly to the sampling circuit 130, andan output of the fifth column line C5 and an output of the seventhcolumn line C7 are combined and provided accordingly to the samplingcircuit 130.

As described above, in the image sensor 2, the first, second and thirdrow selection lines SEL, SELX and SELY separated from one another areprovided in each row of the pixel array 110. Each pair of upper andlower pixels (e.g., P101 and P108), all of which are used in the binningmode operation, are connected to the first row selection line SEL. Eachpair of a lower pixel (e.g., P110) which is used in the binning modeoperation and an upper pixel (e.g., P103) which is not used in thebinning mode operation are connected to the second row selection lineSELX. Each pair of an upper pixel (e.g., P104) which is used in thebinning mode operation and a lower pixel (e.g., P111) which is not usedin the binning mode operation are connected to the third row selectionline SELY.

Accordingly, as described above, in the image sensor 2, pixels used toform each unit pixel in the binning mode operation are the same as thosein the image sensor 1 described above. Therefore, the image sensor 2 canalso perform WDR reliably in the binning mode operation.

In FIG. 11, each row of the pixel array 110 is controlled by thetransfer control signal TG(i), TG(i+1), TG(i+2) or TG(i+3). However,example embodiments are not limited thereto. As described above, eachrow of the pixel array 110 may also be controlled by a signal providedto the first, second and third row selection lines SEL, SELX and SELY.Since this has been fully described above, a redundant descriptionthereof will be omitted.

An image sensor according to another example embodiment will now bedescribed with reference to FIGS. 12 through 17.

FIG. 12 is a circuit diagram of an image sensor 3 according to anotherexample embodiment. FIG. 13 is a diagram illustrating a structure ofsensing pixels included in a pixel array 210 of FIG. 12. FIG. 14 is adiagram illustrating the structure of phase-difference detection pixelsincluded in the pixel array 210 of FIG. 12. FIGS. 15 through 17 arediagrams illustrating a process of performing auto-focusing using thephase-difference detection pixels of FIG. 14. For simplicity, aredundant description of elements identical to those of FIGS. 2-11 willbe omitted.

Referring to FIG. 12, the pixel array 210 of the image sensor 3 mayinclude sensing pixels P201 through P204, P206 through P211, and P213through P228 and phase-difference detection pixels P205 and P212.

Referring to FIG. 13, each of adjacent sensing pixels (e.g., P201 andP202) may include a microlens 31, a surface layer 32, a color filterlayer 33, a wiring layer 34, a photodiode layer 35, and a substratelayer 36. In FIG. 13, cross-sections of the adjacent sensing pixels(e.g., P201 and P202) are schematically illustrated, but exampleembodiments are not limited to the illustration of FIG. 13.

Light from a subject is induced to the photodiode layers 35 of theadjacent sensing pixels (e.g., P201 and P202) by the microlenses 31. Inresponse to the light, photodiodes included in the photodiode layers 35may generate electric charges, thereby producing pixel information. Theelectric charges generated by the photodiode layers 35 may be outputthrough the wiring layer 34. The light from the subject may be incidentas the whole light that passed through an exit pupil of a photographinglens, and luminance information corresponding to the position of thesubject may be obtained from a corresponding pixel position. Threecolors (red, green and blue) may be used in each pixel as the colorfilter layer 33. However, cyan (C), magenta (M) and yellow (Y) may alsobe used if necessary.

Referring to FIG. 14, each of the phase-difference detection pixels P205and P212 may include a microlens 41, a surface layer 42, a color filterlayer 43, a wiring layer 44, a photodiode layer 45, a substrate layer46, and a mask 47 or 48. That is, the phase-difference detection pixelsP205 and P212 may further include the masks 47 and 48 compared with thesensing pixels described above with reference to FIG. 13.

The phase-difference detection pixels P205 and P212 may include afirst-type pixel AFR and a second-type pixel AFL. The first-type pixelAFR may be a right pixel for detecting a phase difference, and thesecond-type pixel AFL may be a left pixel. The right mask 47 may bedisposed between the microlens 41 and the photodiode 45, and the leftmask 48 may be disposed between the microlens 41 and the photodiode 45of the second-type pixel AFL.

The positions of the masks 47 and 48 are not limited to the positionsillustrated in FIG. 14 and can be changed as long as the masks 47 and 48are disposed between the microlens 41 and the photodiode 45. In someexample embodiments, the mask 47 of the first-type pixel AFR may beplaced on the left side of the photodiode 45, and the mask 48 of thesecond-type pixel AFL may be placed on the right side of the photodiode45. However, example embodiments are not limited thereto.

In FIG. 14, optical axes S1 and S2 of the microlenses 41 are indicatedby alternated long and short dash lines, and the paths of light incidentfrom the microlenses 41 are indicated by dotted lines. The masks 47 and48 of FIG. 14 may respectively limit light incident upon the photodiodes45 from pupils 52 and 54 to 50% of the photodiodes 45 with respect tothe optical axes S1 and S2 of the microlenses 41.

When the position of a pixel does not match the optical axis S1 or S2 ofthe photographing lens S1 or 53, the position of the mask 47 or 48 maybe changed.

The image sensor 3 may perform auto focusing using the phase-differencedetection pixels P205 and P212 as will be described in greater detailbelow with reference to FIGS. 15 through 17.

Referring to FIG. 15, light from a subject may pass through aphotographing lens 21 and then enter a right light-receiving pixel 25and a left light-receiving pixel 26 via a microlens column 24. Masks 27and 28 that limit light incident from pupils 22 and 23 of thephotographing lens 21 may be placed in a portion of the rightlight-receiving pixel 25 and a portion of the left light-receiving pixel26. In addition, light from the pupil 22 located above an optical axis29 of the photographing lens 21 among the pupils 22 and 23 of thephotographing lens 21 may enter the left light-receiving pixel 26, andlight from the pupil 23 located under the optical axis 29 of thephotographing lens 21 may enter the right light-receiving pixel 25. Theright light-receiving pixel 25 and the left light-receiving pixel 26 maybe the phase-difference detection pixels P205 and P212 described above.

The image sensor 3 may perform auto focusing based on output valuesgenerated by light incident on the right light-receiving pixel 25 andthe left light-receiving pixel 26. Specifically, referring to FIG. 16,when there is a phase difference between an output value of the rightlight-receiving pixel 25 and an output value of the left light-receivingpixel 26 according to the position of the right light-receiving pixel 25and the position of the left light-receiving pixel 26, the image sensor3 may perform auto focusing. Referring to FIG. 17, when there is nophase difference between an output value of the right light-receivingpixel 25 and an output value of the left light-receiving pixel 26according to the position of the right light-receiving pixel 25 and theposition of the left light-receiving pixel 26, the image sensor 3 maystop auto focusing.

In the image sensor 3, the sensing pixels P219 and P226 which share acolumn line C5 with the phase-difference detection pixels P205 and P212are connected to a second row selection line SELX.

Specifically, referring to FIG. 12, the phase-difference detectionpixels P205 and P212 and the sensing pixels P201 through P204, P206through P211, P213 through P218, P220 through P225, P227 and P228 whichdo not share the column line C5 with the phase-difference detectionpixels P205 and P212 may be connected to a first row selection line SEL,and the sensing pixels P219 and P226 which share the column line C5 withthe phase-difference detection pixels P205 and P212 may be connected tothe second row selection line SELX.

A column selecting circuit 220 may include a column selecting signalgenerator 222 which generates a first column selection signal AVG and asecond column selection signal AVGX. The first column selection signalAVG may be used to combine outputs of the sensing pixels P201 throughP204, P206 through P211, P213 through P218, P220 through P225, P227 andP228 in the binning mode operation as described above. However, thesecond column selection signal AVGX may be used to generate a unit pixelrelated only to outputs of the phase-difference detection pixels P205and P212 in the binning mode operation.

In FIG. 12, the column selecting signal generator 222 is included withinthe column selecting circuit 220, but example embodiments are notlimited thereto. The first column selection signal AVG and the secondcolumn selection signal AVGX may not be generated by the columnselecting circuit 220 but may be provided by, e.g., a row scanningcircuit 150.

The operation of the image sensor 3 will now be described in greaterdetail with reference to FIGS. 18 and 19.

First, the full mode operation of the image sensor 3 will be describedwith reference to FIGS. 12 and 18.

FIG. 18 is a timing diagram illustrating the full mode operation of theimage sensor 3 of FIG. 12.

Referring to FIGS. 12 and 18, in section AA, a transfer control signalTG(i) for an i^(th) row is provided. In addition, a high-level signal isprovided to the first and second row selection lines SEL and SELX.Accordingly, image signals output from the sensing pixels P201 throughP204, P206 and P207 disposed in the i^(th) row and a phase-differencedetection signal output from the phase-difference detection pixel P205are output along first through seventh column lines C1 through C7.

In the section AA, since the first column selection signal AVG and thesecond column selection signal AVGX are at a low level, all of firstthrough third switches S1 through S3 included in the column selectingcircuit 220 are off. Therefore, outputs of the first through seventhcolumn lines C1 through C7 are provided to the sampling circuit 130without being combined with each other.

In section BB, the same operation as the operation performed in thesection AA is performed, and thus a detailed description thereof will beomitted.

In section CC, a transfer control signal TG(i+2) for an (i+2)^(th) rowis provided. In addition, a high-level signal is provided to the firstand second row selection lines SEL and SELX. Accordingly, image signalsoutput from the sensing pixels P215 through P221 disposed in the(i+2)^(th) row are output along the first through seventh column linesC1 through C7.

In the section CC, since the first column selection signal AVG and thesecond column selection signal AVGX are at a low level, all of the firstthrough third switches S1 through S3 included in the column selectingcircuit 220 are off. Therefore, outputs of the first through seventhcolumn lines C1 through C7 are provided to the sampling circuit 130without being combined with each other.

In section DD, the same operation as the operation performed in thesection CC is performed, and thus a detailed description thereof will beomitted.

As described above, the image sensor 3 can perform the full-modeoperation, that is, perform image sensing using outputs of all sensingpixels P201 through P204, P206 through P211 and P213 through P228 andthe phase-difference detection pixels P205 and P212 included in thepixel array 210.

The binning mode operation of the image sensor 3 will now be describedwith reference to FIGS. 12, 19 and 20.

FIG. 19 is a timing diagram illustrating the binning mode operation ofthe image sensor 3 of FIG. 12. FIG. 20 is a diagram illustrating pixelarrangement in a case where the image sensor 3 of FIG. 12 performs thebinning mode operation.

The binning mode operation of the image sensor 3 will now be describedusing a 2×2 binning mode operation as an example, but exampleembodiments are not limited to this example.

The pixels P201 through P228 illustrated in FIG. 12 may be divided intounit pixels in the 2×2 binning mode operation as shown in Table 3 below.

TABLE 3 Unit Pixel UPpq (p is a row, and q is a column) Pixels IncludedUP11 P201~P203 P208~P210 P215~P217 UP12 P202~P204 P209~P211 P216~P218UP13 P205~P207 P212~P214 P219~P221 UP21 P208~P210 P215~P217 P222~P224UP22 P209~P211 P216~P218 P223~P225 UP23 P212~P214 P219~P221 P226~P228

Referring to FIGS. 12 and 19, in section EE, the transfer controlsignals TG(i) and TG(i+2) for the i^(th) row and the (i+2)^(th) row areprovided. In addition, a high-level signal is provided to the first rowselection line SEL, and a low-level signal is provided to the second rowselection line SELX.

In the section EE, since the first column selection signal AVG is at ahigh level and the second column selection signal AVGX is at a lowlevel, the first and second switches S1 and S2 included in the columnselecting circuit 220 are on, but the third switch S3 is off.

Therefore, only an output of the phase-difference detection pixel P205is considered as an output of a unit pixel UP13. Specifically, since alow-level signal is provided to the second row selection line SELX, anoutput of the sensing pixel 219 is not provided to the column line C5.In addition, since the second column selection signal AVGX is at a lowlevel, the third switch S3 is turned off. Therefore, outputs of thesensing pixels 207 and 221 connected to the seventh column line C7 arenot combined. That is, only an output of the phase-difference detectionpixel P205 is considered as an output of the unit pixel UP 13, asillustrated in FIG. 20.

Outputs of the sensing pixels P201 through P204 and P215 through P218are combined, and the combined outputs are considered as outputs ofother unit pixels UP11 and UP12. Since this has been fully describedabove, a detailed description thereof will be omitted.

In section FF, transfer control signals TG(i+1) and TG(i+3) for an(i+1)^(th) row and an (i+3)^(th) row are provided. In addition, ahigh-level signal is provided to the first row selection line SEL, and alow-level signal is provided to the second row selection line SELX.

In the section FF, since the first column selection signal AVG is at ahigh level and the second column selection signal AVGX is at a lowlevel, the first and second switches S1 and S2 included in the columnselecting circuit 220 are on, but the third switch S3 is off.

Therefore, only an output of the phase-difference detection pixel P212is considered as an output of a unit pixel UP23. Specifically, since alow-level signal is provided to the second row selection line SELX, anoutput of the sensing pixel 226 is not provided to the column line C5.In addition, since the second column selection signal AVGX is at a lowlevel, the third switch S3 is turned off. Therefore, outputs of thesensing pixels 214 and 228 connected to the seventh column line C7 arenot combined. That is, only an output of the phase-difference detectionpixel P212 is considered as an output of the unit pixel UP23, asillustrated in FIG. 20.

Outputs of the sensing pixels P208 through P211 and P222 through P225are also combined, and the combined outputs are considered as outputs ofother unit pixels UP21 and UP22. Since this has been fully describedabove, a detailed description thereof will be omitted.

Based on these operations, pixels used in the binning mode operation maybe summarized by each unit pixel as shown in Table 4 below.

TABLE 4 Unit Pixel Pixels Used UP11(section EE) P201, P203 P215, P217UP12(section EE) P202, P204 P216, P218 UP13(section EE) P205UP21(section FF) P208, P210 P222, P224 UP22(section FF) P209, P211 P223,P225 UP23(section FF) P212

In the image sensor 3, the first and second row selection lines SEL andSELX separated from each other are provided in each row of the pixelarray 210, and the first through third switches S1 through S3 includedin the column selecting circuit 220 are turned on or off using the firstand second column selection signals AVG and AVGX. Therefore, the imagesensor 3 can perform auto focusing even in the binning mode operationusing the unit pixels UP11 through UP13 and UP21 through UP23. That is,auto focusing can be performed reliably even in the binning modeoperation without the addition of a circuit, which can increase themanufacturing cost of a product, to the image sensor 3.

In FIG. 19, each row of the pixel array 210 is controlled by thetransfer control signal TG(i), TG(i+1), TG(i+2) or TG(i+3). However,example embodiments are not limited thereto. As described above, eachrow of the pixel array 210 may also be controlled by a signal providedto the first and second row selection lines SEL and SELX. Since this hasbeen fully described above, a detailed description thereof will beomitted.

An image sensor according to another example embodiment will now bedescribed with reference to FIG. 21.

FIG. 21 is a circuit diagram of an image sensor 4 according to anotherexample embodiment. FIG. 21 will be described, focusing mainly ondifferences with FIGS. 2-20.

Referring to FIG. 21, in the image sensor 4, one row selection line SELis provided in each row. In other words, each row of a pixel array 310is connected to a row scanning circuit 350 by one row selection lineSEL.

In the image sensor 4, first and second column selection lines C1-1through C7-2 separated from each other are provided in each column. Inaddition, sensing pixels P201 through P204, P206 through P211 and P213through P228 and phase-difference detection pixels P205 and P212 areconnected to different column selection lines as illustrated in thedrawing.

Specifically, all of the sensing pixels P201, P208, P215 and P222disposed in a first column may be connected to the first columnselection line C1-1, all of the sensing pixels P202, P209, P216 and P223disposed in a second column may be connected to the first columnselection line C2-1, all of the sensing pixels P203, P210, P217 and P224disposed in a third column may be connected to the first columnselection line C3-1, all of the sensing pixels P204, P211, P218 and P225disposed in a fourth column may be connected to the first columnselection line C4-1, all of the sensing pixels P219 and P226 disposed ina fifth column may be connected to the first column selection line C5-1,all of the sensing pixels P206, P213, P220 and P227 disposed in a sixthcolumn may be connected to the first column selection line C6-1, and allof the sensing pixels P207, P214, P221 and P228 disposed in a seventhcolumn may be connected to the first column selection line C7-1.

All of the phase-difference detection pixels P205 and P212 disposed inthe fifth column may be connected to the second column selection lineC5-2.

A column selecting circuit 320 may include a plurality of switches S 11through S17 which can select the first and second column selection linesC1-1 through C7-2. A selecting signal generator (e.g. 122) may generatesignals to control the switches 511 through 517.

The image sensor 4 structured as described above can perform autofocusing even in a binning mode operation. Specifically, in the binningmode operation, the eleventh through fourteenth switches S11 through S14and the sixteenth switch S16 may be connected to the first columnselection lines C1-1 through C4-1 and C6-1, and the fifteenth switch S15and the seventeenth switch S17 may be connected to the second columnselection lines C5-2 and C7-2. In this case, unit pixel outputs can beobtained as illustrated in FIG. 20. That is, by connecting the fifteenthswitch S15 and the seventeenth switch S17 to the second column selectionlines C5-2 and C7-2, outputs of the phase-difference detection pixelsP205 and P212 only may be considered as outputs of the unit pixels UP13and UP23.

Therefore, the image sensor 4 can perform auto focusing in the binningmode operation.

FIG. 22 is a block diagram of an example of a digital camera 800 usingan image sensor according to example embodiments.

Referring to FIG. 22, the digital camera 800 may include a lens 810, animage sensor 820, a motor unit 830, and an engine unit 840. The imagesensor 820 may be any one of the image sensors according to theabove-described example embodiments in FIGS. 1-21.

The lens 810 focuses incident light onto a light-receiving region of theimage sensor 820. The image sensor 820 may generate RGB data RGB in aBayer pattern based on the light received through the lens 810. Theimage sensor 820 may provide the RGB data RGB based on a clock signalCLK.

In some example embodiments, the image sensor 820 may interface with theengine unit 840 using a mobile industry processor interface (MIPI)and/or a camera serial interface (CSI).

The motor unit 830 may adjust the focus of the lens 810 or performshuttering in response to a control signal CTRL received from the engineunit 840. The engine unit 840 may control the image sensor 820 and themotor unit 830. In addition, the engine unit 840 may generate YUV dataYUV including a luminance component, a difference between the luminancecomponent and a blue component and a difference between the luminancecomponent and a red component or generate compressed data, e.g., JointPhotography Experts Group (JPEG) data based on the RGB data RGB receivedfrom the image sensor 820.

The engine unit 840 may be connected to a host/application 850 and mayprovide the YUV data YUV or the JPEG data to the host/application 850based on a master clock MCLK. In addition, the engine unit 840 mayinterface with the host/application 850 using a serial peripheralinterface (SPI) and/or an inter-integrated circuit (I²C).

FIG. 23 is a block diagram of an example of a computing system 1000using an image sensor according to example embodiments.

Referring to FIG. 23, the computing 1000 may include a processor 1010, amemory device 1020, a storage device 1030, an input/output (I/O) device1040, a power supply 1050, and an image sensor 1060.

The image sensor 1060 may be any one of the image sensors according tothe above-described example embodiments in FIGS. 1-21. Althoughillustrated in FIG. 23, the computing system 1000 may further includeports that can communicate with a video card, a sound card, a memorycard, a USB device, or other electronic devices.

The processor 1010 may perform various calculations or tasks. Accordingto example embodiments, the processor 1010 may be a microprocessor or acentral processing unit (CPU).

The processor 1010 may communicate with the memory device 1020, thestorage device 1030 and the I/O device 1040 through an address bus, acontrol bus, and a data bus.

According to example embodiments, the processor 1010 may be coupled toan extended bus, such as a peripheral component interconnection (PCI)bus.

The memory device 1020 may store data required for the operation of thecomputing system 1000.

For example, the memory device 1020 may be implemented as a dynamicrandom access memory (DRAM), a mobile DRAM, a static random accessmemory (SRAM), a phase random access memory (PRAM), a ferroelectricrandom access memory (FRAM), a resistive random access memory (RRAM),and/or a magnetic random access memory (MRAM). The storage device 1030may include a solid state drive (SSD), a hard disk drive (HDD), aCD-ROM, etc.

The I/O device 1040 may include an input device (e.g., a keyboard, akeypad, a mouse, etc.) and an output device (e.g., a printer, a display,etc.). The power supply 1050 may supply an operating voltage requiredfor the operation of the computing system 1000.

The image sensor 1060 may be connected to and communicate with theprocessor 1010 via buses or other communication links. The image sensor1060 and the processor 1010 may be integrated together onto a singlechip or may be integrated separately onto different chips, respectively.

The computing system 1000 may be any type of computing system using animage sensor. For example, the computing system 1000 may be a digitalcamera, a mobile phone, a personal digital assistant (PDA), a portablemultimedia player (PMP), a smart phone, a table PC, etc.

In some example embodiments, the computing system 1000 may be an UltraMobile PC (UMPC), a work station, a net-book, a portable computer, awireless phone, a mobile phone, an e-book, a portable game console, anavigation device, a black box, a 3-dimensional television, a digitalaudio recorder, a digital audio player, a digital picture recorder, adigital picture player, a digital video recorder, a digital videoplayer, etc.

FIG. 24 is a block diagram illustrating an example of interfaces used inthe computing system of FIG. 23.

Referring to FIG. 24, a computing system 1100 may be implemented as adata processing device that uses or supports a mobile industry processorinterface (MIPI). The computing system 1100 may include an applicationprocessor 1110, an image sensor 1140 and a display 1150.

A camera serial interface (CSI) host 1112 of the application processor1110 may perform serial communication with a CSI device 1141 of theimage sensor 1140 via a CSI.

In some example embodiments, the CSI host 1112 nay include adeserializer (DES), and the CSI device 1141 may include a serializer(SER). A display serial interface (DSI) host 1111 of the applicationprocessor 1110 may perform serial communication with a DSI device 1151of the display 1150 via a DSI.

In some example embodiments, the DSI host 1111 may include an SER, andthe DSI device 1151 may include a DES. The computing system 1100 mayfurther include a radio frequency (RF) chip 1160 which can communicatewith the application processor 1110. A physical layer (PHY) 1113 of thecomputing system 1100 and a PHY 1161 of the RF chip 1160 may performdata communications based on a MIPI DigRF.

The application processor 1110 may further include a DigRF MASTER 1114which controls the data communication of the PHY 1161 based on the MIPIDigRF. The computing system 1100 may further include a globalpositioning system (GPS) 1120, a storage 1170, a microphone 1180, a DRAM1185, and a speaker 1190. In addition, the computing system 1100 mayperform communications using an ultra wideband (UWB) 1120, a wirelesslocal area network (WLAN) 1220, a worldwide interoperability formicrowave access (WIMAX) 1230, etc. However, the above structure andinterfaces of the computing system 100 are merely an example, andexample embodiments are not limited to this example.

In concluding the detailed description, those skilled in the art willappreciate that many variations and modifications can be made to exampleembodiments without substantially departing from the principles ofexample embodiments. Therefore, the disclosed example embodiments areused in a generic and descriptive sense only and not for purposes oflimitation.

What is claimed is:
 1. An image sensor comprising: a pixel arrayincluding, a plurality of pixels including at least a first pixel and asecond pixel, first and second row selection lines separated from eachother, and first and second column lines separated from each other; anda column selecting circuit configured to connect the first and secondcolumn lines using a column selection signal, the first pixel beingconnected to the first row selection line and the first column line, andthe second pixel being in the same row as the first pixel and connectedto the second row selection line and the second column line.
 2. Theimage sensor of claim 1, wherein the column selecting circuit isconfigured to output a signal to a sampling circuit, the samplingcircuit including an analog-to-converter (ADC).
 3. The image sensor ofclaim 1, wherein the first pixel includes, a first drive transistorconfigured to receive an output of a first photodiode and generate asource-drain current based on the output of the first photodiode, and afirst select transistor connected to the first row selection line andconfigured to provide an output of the first drive transistor to thefirst column line, and the second pixel includes, a second drivetransistor configured to receive an output of a second photodiode andgenerate a source-drain current based on the output of the secondphotodiode, and a second select transistor connected to the second rowselection line and configured to provide an output of the second drivetransistor to the second column line.
 4. The image sensor of claim 1,wherein the plurality of pixels are in a Bayer pattern.
 5. The imagesensor of claim 4, further comprising: a control circuit configured tosupply at least one control signal to the first pixel and the secondpixel such that the first pixel has a longer exposure time than anexposure time of the second pixel.
 6. The image sensor of claim 5,wherein the plurality of pixels are in a chess mosaic pattern.
 7. Theimage sensor of claim 4, wherein the pixel array further comprises: athird pixel connected to the first column line and the second rowselection line, wherein the first and second pixels include sensingpixels, and the third pixel includes a phase-difference detection pixel.8. The image sensor of claim 7, wherein the pixel array further includesthird and fourth column lines separated from the first and second columnlines, the column selection signal includes first and second columnselection signal parts, and the column selecting circuit is configuredto connect the first and second column lines using the first columnselection signal part and connect the third and fourth column linesusing the second column selection signal part.
 9. The image sensor ofclaim 1, further comprising: a third row selection line separated fromthe first and second row selection lines; a third column line separatedfrom the first and second column lines; and the plurality of pixelsincludes a third pixel, the third pixel being in the same row of thepixel array as the first pixel and connected to the third row selectionline and the third column line.
 10. The image sensor of claim 9, whereineach of the first, second and third pixels comprises a first subpixeland a second subpixel, and the first subpixel and the second subpixelshare a select transistor.
 11. An image sensor comprising: a pixel arrayincluding, a plurality of pixels, first and second row selection linesseparated from each other, and column lines intersecting the first andsecond row selection lines; a row scanning circuit configured to controlthe first and second row selection lines; and a sampling circuitconfigured to receive outputs of the column lines and convert thereceived outputs into digital signals, the first and second rowselection lines being in each row of the pixel array, and at least oneselect transistor in a number of the plurality of pixels is connected toone of the first and second row selection lines.
 12. The image sensor ofclaim 11, wherein the column lines include first and second column lineswhich are separated from each other, and the image sensor furthercomprises: a column selecting circuit configured to connect the firstand second column lines using a column selection signal and to connectthe connected first and second column lines to the sampling circuit. 13.The image sensor of claim 12, wherein the column lines further includesthird and fourth column lines which are separated from the first andsecond column lines, the column selection signal includes a first columnselection signal part and a second column selection signal part, and thecolumn selecting circuit is configured to connect the first and secondcolumn lines based on the first column selection signal part and toconnect the third and fourth column lines based on the second columnselection signal part.
 14. The image sensor of claim 13, wherein pixelsconnected to the first through third column lines are all connected tothe first row selection line, and pixels connected to the fourth columnline include a first pixel connected to the first row selection line anda second pixel connected to the second row selection line.
 15. The imagesensor of claim 14, wherein the first pixel includes a phase-differencedetection pixel, and the second pixel includes a sensing pixel.
 16. Animage sensor comprising: a pixel array having rows and columns ofpixels, the rows connected to first and second selection lines and thepixel array having first exposure pixels and second exposure pixels; acontrol circuit configured to supply at least one control signal to thepixels such that an exposure time of the first exposure pixels isgreater than an exposure time of the second exposure pixels; and acolumn selecting circuit configured to connect a number of the columnsof pixels based on an operating mode of the image sensor.
 17. The imagesensor of claim 16, further comprising: a row scanning circuitconfigured to output selection signals to the first and second selectionlines, respectively, the column selecting circuit configured to combineoutputs of only the first exposure pixels based on the selection signalsand to combine outputs of only the second exposure pixels based on theselection signals.
 18. The image sensor of claim 16, wherein theoperating mode is one of a binning mode and a non-binning mode.
 19. Theimage sensor of claim 16, wherein two pixels in a same column areconnected to a same selection line.
 20. The image sensor of claim 16,wherein the pixel array further includes a third selection line, and afirst pixel in a first row and a second pixel in the second row areconnected to the third selection line.